As Application Specific Integrated Circuit (ASIC) technologies expand into new markets, the need for denser embedded memory generally increases. For example, markets in portable and multimedia applications such as cellular phones and personal digital assistants generally demand increased density of embedded memory for higher function and lower power consumption. In order to accommodate this increased demand, embedded dynamic random access memory (eDRAM) macros have been offered in state-of-the-art ASIC portfolios. The integration of eDRAM into ASIC designs generally has intensified the focus on how best to test high-density macros, such as a complex DRAM macro, in a logic test environment.
For example, direct memory access (DMA) testing generally may be used to test conventional DRAMs, which have pads for direct control of address, data and control pins that are accessible by an external tester. The external tester may directly manipulate the DRAM inputs and monitor the outputs for testing. Direct access testing for embedded eDRAM, or other types of embedded RAM such as embedded magnetic RAM (MRAM) and embedded flash RAM, however, generally is too costly in terms of silicon area, available input/output (I/O) pins, wiring complexity and test time. For example, with embedded RAM, the only access to the RAM generally is through the system application in which the RAM is embedded. To require the application to also function as the tester generally may require extra memory storage or extra I/O pins for external access.
Generally, a preferred solution to the embedded-device test problem is the use of a built-in self test (BIST) system that implements elements sufficient for high-fault coverage on DRAM. Such elements may include, for example, the calculation of a two-dimensional redundancy solution, pattern programming flexibility, real-time or at-speed testing, and test mode application for margin testing. The development of BIST capabilities generally has allowed the testing of large, embedded memories on logic testers without the added die area or performance testing inaccuracies associated with, e.g., isolation multiplexers.
Generally, the BIST is a relatively simple circuit (although it may be complicated) that functions like a small tester on the semiconductor chip or integrated circuit. The BIST may be designed to have partial or full access to the embedded RAM, while the external automated test equipment generally has only very limited access to the chip, and relies on the BIST to carry out the detailed testing of the memory. The BIST may test only the core memory component because the chip's logic circuitry may be tested by a separate logic tester.
Because the BIST is on the die and can directly control the embedded RAM, a designer may design various levels of functionality between the BIST and the actual device circuitry, such as different test modes. To test the embedded RAM, the external tester may send a command to the BIST to initiate a test. Generally, when the BIST completes the test, it returns to the external tester a value indicating whether the device passed or failed the test. For example, a logic 0 may indicate that the DRAM passed the test and a logic 1 may indicate that the DRAM failed the test, or vice versa.
One potential drawback associated with existing BIST implementations is that there is only limited information from the BIST test available externally to the chip. Generally, the external tester may be used only for initial BIST test program vector and clock input, and for monitoring the very limited BIST output, such as a fail flag pin and an end-of-test (EOT) pin. Generally, once a test is initiated, the on-chip BIST internally generates addresses and data patterns sent to the embedded RAM, and internally compares data returned from the embedded RAM. If the device fails the test, then the BIST may flag the failure on a designated external pin, such as by setting the fail signal to a logic one to indicate a fail, or hold a logic zero to indicate a pass.
From the perspective of the external tester, the only information received from the BIST is whether the entire test was passed or failed by the device. In other words, the external tester receives the same result regardless of whether a single memory address on the chip fails, or the entire memory array fails, and the external tester cannot distinguish between the two, nor pinpoint the cause of the failure.